Emerging next generation wireless systems will require new protocols and implementations that can support the exponential increase in number of connected devices and 100s of gigabits of data transmission and reception on resource constrained wireless channels. Full-duplex communication has recently been proposed to improve spectrum usage by enabling simultaneous reception and transmission on the same frequency band with a goal to potentially double spectrum efficiency. However, full-duplex communication requires significant innovation in mitigating interference of the transmitted signal into the receive path of the transceiver. Additionally, cross-interference from additional simultaneous uplink and downlink communications affect network performance limiting spectral efficiency gains. MIMO coupled with full-duplex communication complicates communication system design multi-fold. Field trials have shown the viability of full-duplex communication; however, practical VLSI implementation of both analog and digital signal processing to mitigate interference with low-area and high energy-efficiency are challenging research problems. The focus of this symposium is to present new research on advanced and novel signal processing techniques and low-cost implementations that can enhance both analog RF and digital baseband components of the radio to greatly limit linear and non-linear interference – self and multi-user – to meet the required amount of cancellation to enable full-duplex communication.
Intel Corporation, USA
In this talk we present enabling technologies for full-duplex (FD) MIMO. For self-interference cancellation, we have introduced adaptive echo cancellation concept which is based on adaptive filter theory. First, open loop technique is compared to closed loop technique. Closed loop technique such as adaptive echo cancellation continuously updates the system parameters even without requiring special training signal and synchronizations such as OFDM boundary, resulting fast and continuous tracking even during random data transmission. In addition, even in the presence of stronger desired received signal than self-interference, it provides stable tracking and continuous self-interference cancellation. Secondly, in MIMO, the SIC complexity increases exponentially. We propose simpler architecture for RF cancellation which requires only one extra downconverter regardless of the number of taps without performance loss. For digital cancellation, bilinear architecture is proposed. RF components can be modeled by a linear combination of kernels. In non-bilinear, an adaptive filter is applied at each kernel. Hence, parallel adaptive filters are required. However, in bilinear architecture, two adaptations are cascaded: one for non-linear RF component modeling and the other for echo channel. Although this architecture significantly reduces the complexity, it has stability issues and creates too large dynamics of intermediate variables which prevent from efficient HW implementation. We have solved these short comings and will show demo videos of 2x2 MIMO FD system exhibiting that residual self-interference is below noise.
Yang-Seok Choi received the B.S. degree from Korea University, Seoul, South Korea, in 1990, the M.S.E.E. degree from the Korea Advanced Institute of Science and Technology, Taejon, South Korea, in 1992, and the Ph.D. degree from Polytechnic University, Brooklyn, NY, in 2000, all in Electrical Engineering. From 1992 to 1996, Dr. Choi was with Samsung Electronics, Co., Ltd., Suwon, Korea, where he developed 32-QAM modem for HDTV and QPSK ASIC for DBS. In 2000, Dr. Choi joined National Semiconductor, East Brunswick, NJ, where he was involved in the development of W-CDMA. During 2001–2002, Yang-seok was a Senior Technical Staff Member at AT&T Labs-Research, Middletown, NJ where he researched MIMO systems, OFDM systems and information theory. From 2002 to 2004 Dr. Choi was with ViVATO, Inc., Spokane, WA, working on MIMO OFDM systems, smart antenna systems, and antenna/beam selection techniques. In 2004, Dr. Yang-seok Choi joined Intel Corporation, Hillsboro, OR where his research focuses on next generation wireless communications systems, with a focus on full-duplex communication and interference cancellation. His additional research interests include MIMO, OFDM, MC-CDMA, smart antenna, blind identification/equalizer, carrier/timing recovery, space-time coding, cross-layer design and capacity of time-varying multipath channel. Dr. Choi holds several U.S. patents.
Columbia University, USA
Full duplex wireless has attracted significant research attention in the last five years due to its ability to potentially double network capacity at the physical layer, while offering numerous benefits at the higher layers. The basic challenge in full duplex is the tremendous transmitter self-interference at the receiver, which can be one trillion times more powerful than the desired signal and must be dealt with in all domains. There has been significant work on prototype full-duplex radios using off-the-shelf components and showing the feasibility of self-interference cancellation, and on network-layer implications of full-duplex operation.
However, the implementation of integrated full-duplex radios in commercial CMOS processes, necessary for widespread deployment, particularly in small-form-factor devices, is fraught with several fundamental challenges. Integrated CMOS electronics typically exhibit much lower dynamic range than off-the-shelf components, leading to several challenges related to full-duplex operation, including noise and distortion added by the transceiver or by the cancellers, and the bandwidth associated with the cancellation. Furthermore, shared antenna interfaces for full-duplex, such as circulators, are either impossible to integrate on chip due to a reliance on magnetic (ferrite) materials, or exhibit prohibitive loss and/or linearity penalties.
This talk will introduce several generations of integrated full-duplex transceivers developed at Columbia University that address these problems. I will discuss RF self-interference cancellation concepts that add minimal noise and distortion penalty, and are able to achieve wideband cancellation across antenna interfaces with significant frequency selectivity. At the electromagnetic (i.e. antenna) interface, I will talk about our recent work on breaking Lorentz Reciprocity using time-variance to realize the first integrated magnetic-free non-reciprocal circulator. I will also discuss how polarization can be utilized to achieve robust self-interference suppression by embedding complex signal processing functionalities like wireless channel equalization in the antenna domain. Finally, I will discuss how joint self-interference suppression across the antenna, RF/analog and digital domains can enable achievement of the 90-100dB self-interference suppression levels in integrated full-duplex radios.
Harish Krishnaswamy received the B.Tech. degree in electrical engineering from the Indian Institute of Technology, Madras, India, in 2001, and the M.S. and Ph.D. degrees in electrical engineering from the University of Southern California (USC), Los Angeles, CA, USA, in 2003 and 2009, respectively. In 2009, he joined the Electrical Engineering Department, Columbia University, New York, NY, USA, where he is currently an Associate Professor. His research interests broadly span integrated devices, circuits, and systems for a variety of RF, mmWave and sub-mmWave applications. Dr. Krishnaswamy serves as a member of the Technical Program Committee (TPC) of several conferences, including the IEEE International Solid-State Circuits Conference (2015/16-present) and IEEE RFIC Symposium (2013-present). He was the recipient of the IEEE International Solid-State Circuits Conference (ISSCC) Lewis Winner Award for Outstanding Paper in 2007, the Best Thesis in Experimental Research Award from the USC Viterbi School of Engineering in 2009, the Defense Advanced Research Projects Agency (DARPA) Young Faculty Award in 2011, a 2014 IBM Faculty Award and the 2015 IEEE RFIC Symposium Best Student Paper Award - 1st Place. He is serving as a Distinguished Lecturer of the IEEE SSCS over 2017-2018.
|Wednesday, November 15|
|09:40 - 10:30|
|FDX-DST.1: Distinguished Speaker - Yang-Seok Choi, Intel Corporation, USA|
|11:00 - 12:30|
|FDX-O.1: Signal Processing for Interference Cancellation and Full-Duplex Communication Systems|
|14:00 - 15:30|
|FDX-P.1: Signal Processing for Interference Cancellation and Full-Duplex Communication Systems Posters|
|Thursday, November 16|
|09:40 - 10:30|
|FDX-DST.2: Distinguished Speaker - Harish Krishnaswamy, Columbia University, USA|
Submissions are welcome on topics including:
Prospective authors are invited to submit full-length papers (up to 4 pages for technical content, an optional 5th page containing only references) and extended abstracts (up to 2 pages, for paperless industry presentations and Ongoing Work presentations). Manuscripts should be original (not submitted/published anywhere else) and written in accordance with the standard IEEE double-column paper template. Accepted full-length papers will be indexed on IEEE Xplore. Accepted abstracts will not be indexed in IEEE Xplore, however the abstracts and/or the presentations will be included in the IEEE SPS SigPort. Accepted papers and abstracts will be scheduled in lecture and poster sessions. Submission is through the GlobalSIP website at http://2017.ieeeglobalsip.org/Papers.asp.
Notice: The IEEE Signal Processing Society enforces a “no-show” policy. Any accepted paper included in the final program is expected to have at least one author or qualified proxy attend and present the paper at the conference. Authors of the accepted papers included in the final program who do not attend the conference will be subscribed to a “No-Show List”, compiled by the Society. The “no-show” papers will not be published by IEEE on IEEEXplore or other public access forums, but these papers will be distributed as part of the on-site electronic proceedings and the copyright of these papers will belong to the IEEE.
|Paper Submission Deadline||June 2, 2017|
|Review Results Announced||July 17, 2017|
|Camera-Ready Papers Due||August 5, 2017|
Warren Gross, McGill University
Farhana Sheikh, Intel Corporation
Zhiyuan Yan, Lehigh University